Study of hardware implementation of neural networks when processing information in residue number system
Abstract
Study of hardware implementation of neural networks when processing information in residue number system
Incoming article date: 25.08.2023This article examines models of arithmetic devices for finite ring neural networks of the second and third orders. The arithmetic devices under study were synthesized on the basis of FPGA. Estimates of hardware costs and performance of computers for system modules of residual classes of different capacity were obtained. The structure of a finite ring neural network with dynamic connections is proposed, the efficiency of which in terms of hardware costs is observed with increasing capacity of the residue number system module. The advantage of a finite ring neural network with dynamic connections is established for modules with a capacity of 64 bits and higher.
Keywords: neural networks, residue number system, group of elliptic curve points, FPGA, multiplier, adder