In this article, the evaluation of the effect of the trace elements on the reliability of the design of the combinational circuit in the field-programmable gate array (FPGA) basis is researched. An evaluation of the reliability of combinational circuits in the basis of three-input FPGA cells, as well as three-input FPGA cells, taking into account the trace elements, is given. Proposed methods for evaluate the reliability of the project at various stages of the development of fault-tolerance projects in the FPGA basis. The use of these methods allows the design of combinational circuits of increased reliability in the basis of reconfigurable integrated circuits without built-in reliability features.

Keywords: reliability, evaluation fault tolerance, combinational circuit, FPGA, fault injection

Currently, issues of development of power efficient hardware blocks for digital signal processing (DSP) devices gain special importance. This is due to the rapid flourishing of wearable electronics, the Internet of things (IoT), network and telecommunication systems. The key component of many DSP devices is a finite impulse response (FIR) filter. It is not surprising that currently a large number of scientific papers are devoted to the development of power efficient FIR filters. The article proposes an original approach to the issue solution. As a methodological basis, modular arithmetic was chosen, already proven as an effective mathematical apparatus for the development of high-speed DSP devices. Another solution was the use of the FIR filter transposed form and methods for constructing the reduced blocks of the multiconstant multipliers. The experimental part demonstrated the efficiency of the block reduction methods of the multiconstant multiplication from the point of view of the filter power consumption. The article also made recommendations for the use of the proposed methods for specific implementations of the FIR filters.

Keywords: modulo FIR filter, multiconstant multiplier, transposed form, power consumption, dissipated power

The crosstalk level increases with increasing degree of circuit integration. At the same time, requirements to their noise immunity increase. The increase in the amplitude of the pulse signals is a simple and effective method to improve noise immunity. The article discusses the synchronization system with the global distribution of low-voltage clock signal and a local increase in the amplitude using drivers with increasing voltage. Proposed technical solutions allow to set the amplitude of the clock signal individually for each functional unit.

Keywords: synchronization, noise immunity, clock signal drivers, amplitude increase, source and power rail reduction